FPGA Implementation of Parallel Adder Using Reversible Logic Gates

Reversible digital technology can now start taking a more desirable direction for low dissipation of power, higher processing speeds. Here, we suggested the construction an 8-, 16-, 32-, 64-bit multiplier using carry-save adder, Kogge stone and HNFG adder with high operating speed proposed gate adder. The architecture device logic gates which are reversible be implemented Vedic multiplier. output accumulator operation is dependent on unit units. development built to achieve speeds, use greater efficiency. Also fewer area partial elements used. A comparative study being conducted between conventional [] based HNFG. Finally, it has been shown that relatively high-speed over method. whole process simulation synthesis done Xilinx 14.7 tool.